PIC24FJ128GA008-I/PT【PDF 9/258 页】IC PIC MCU FLASH 128K 80TQFP

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PIC24FJ128GA010 FAMILY

DS39747F-page 106

2005-2012 Microchip Technology Inc.

9.2.2

IDLE MODE

Idle mode has these features:

The CPU will stop executing instructions.

The WDT is automatically cleared.

The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Selective Peripheral Module Control”

If the WDT or FSCM is enabled, the LPRC will

also remain active.

The device will wake from Idle mode on any of these

events:

Any interrupt that is individually enabled.

Any device Reset.

A WDT time-out.

On wake-up from Idle, the clock is re-applied to the

CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction or the first instruction in the ISR.

9.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV

instruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

9.3

Doze Mode

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

while using a power-saving mode may stop

communications completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at the

same speed, while the CPU clock speed is reduced.

Synchronization between the two clock domains is

maintained, allowing the peripherals to access the SFRs

while the CPU executes code at a slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>).

There

are

eight

possible

configurations, from 1:1 to 1:128, with 1:1 being the

default.

It is also possible to use Doze mode to selectively

reduce power consumption in event driven applica-

tions. This allows clock-sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

9.4

Selective Peripheral Module

Control

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked, and thus, consume power. There may be

cases where the application needs what these modes

do not provide: the allocation of power resources to

CPU processing with minimal power consumption from

the peripherals.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

The Peripheral Enable bit, generically named

“XXXEN”, located in the module’s main control

SFR.

The Peripheral Module Disable (PMD) bit, generi-

cally named “XXXMD”, located in one of the PMD

Control registers.

Both bits have similar functions in enabling or disabling its

associated module. Setting the PMD bit for a module dis-

ables all clock sources to that module, reducing its power

consumption to an absolute minimum. In this state, the

control and status registers associated with the periph-

eral will also be disabled, so writes to those registers will

have no effect and read values will be invalid. Many

peripheral modules have a corresponding PMD bit.

In contrast, disabling a module by clearing its XXXEN

bit disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as the PMD bit does.

Most peripheral modules have an enable bit;

exceptions include Capture, Compare and RTCC.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the

control bit of the generic name format, “XXXIDL”. By

default, all modules that can operate during Idle mode

will do so. Using the disable on Idle feature allows

further reduction of power consumption during Idle

mode, enhancing power savings for extremely critical

power applications.

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